1. Field of Invention
This invention generally relates to fabrication of devices such as micro-electromechanical system (MEMS) devices.
2. Related Art
Process development, control, and monitoring are increasingly important as the dimensions of electronic and micro-electromechanical system (MEMS) devices decrease.
For example, some MEMS devices require accurate, high aspect ratio etch processes so that the resulting structures meet design tolerances. Although many techniques developed for use in the fabrication of electronic devices may be used in fabricating MEMS devices, they may fall short in some circumstances.
For example, although integrated circuitry may be incredibly complex, the physical boundaries of the chips themselves are relatively simple. In the manufacture of integrated circuits (ICs), a single substrate (e.g., semiconductor wafer) may be processed to form a number of ICs. The integrated circuits may then be separated into generally rectangular dice, to be packaged and sold.
By contrast, the physical boundaries of MEMS device structures may be quite complex. Therefore, they present some different challenges than those encountered in the manufacture of electronic devices.
One example of a fabrication process for a MEMS device is shown in FIG. 1A. A 300 micron thick silicon wafer 110 is etched using a photoresist pattern 115 to form the desired device structure. In the example shown, a deep reactive ion etch (DRIE) with a suitable silicon etchant 116 is performed on the wafer. For this etch, the aspect ratio of the etch (the ratio of the depth to the width) can be quite high.
However, the example shown in FIG. 1A has a number of shortcomings from a processing standpoint. Since wafer 110 is etched completely through the wafer, it becomes quite fragile when the etch nears completion. Additionally, DRIE process equipment generally supplies a coolant material 117 to the back side 111 of wafer 110 in order to effectively cool the wafer and obtain acceptable photoresist selectivity values (without cooling, the photoresist can be rapidly removed from the wafer). Once wafer 110 is perforated, the action of coolant 117 becomes ineffective, especially on narrow resultant features. The resulting wafer heating may cause the etch process to deviate from expected results towards the end of the etch. Additionally, once wafer 110 is perforated, the pressure in the etch chamber can rapidly increase due to coolant supply pressures, which may cause damage to the wafer and/or etch equipment.
In order to mitigate these problems, a different process is generally used to manufacture MEMS devices requiring through wafer DRIE processing. FIG. 1B illustrates an example of this process. Rather than using a silicon wafer alone, the process in FIG. 1B uses a silicon wafer 110 attached to a carrier 120 using a bonding layer 130 of an adhesive material such as photoresist or wax.
As in the example of FIG. 1A, devices may be formed by etching structures defined by photoresist pattern 115, using an appropriate silicon etchant 116 in a DRIE process. Coolant 117 is applied to the backside 111 of carrier 120. Once the etch process is complete, the devices need to be released from bonding layer 130. This generally requires a labor-intensive cleaning process.
The process of FIG. 1B also has a number of drawbacks. First, the adhesive used to bond silicon wafer 110 to carrier 120 is generally a poor thermal conductor. Thus, heat from the etch process is not removed efficiently, and the temperature of etched wafer 110 increases as the etch progresses. This can degrade the quality of the etch process and comprise the resulting structure, so that the desired geometry is not obtained (particularly at the bottom of the etched structure formed near the completion of the etch process). Additionally, as noted above, the cleaning process to release structures from bonding layer 130 is labor-intensive, which increases both production time and cost.
In another example, a silicon on insulator (SOI) wafer may be used rather than a silicon wafer bonded to a carrier using adhesive. An SOI wafer has a silicon handle layer, an insulating (oxide) bonding layer, which is referred to as the buried oxide (BOX) layer, and a silicon device layer. Generally, SOI wafers are manufactured with great care, and good quality bonds on large sized wafers are common. The use of an SOI wafer provides a better thermal conduction path during the DRIE etch process (resulting in better conformance of the etched structure to the desired geometry). However, the structures are generally released using a wet etch process that etches the BOX layer. Multiple rinse processes must be performed to remove the liquid etchant (which usually contains hydrofluoric acid or HF) from the structures. The use of a wet etch/rinse process can result in stiction: that is, when the structures dry they tend to stick to each other or the handle wafer. Damage to structures caused by stiction increases the manufacturing costs.